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Standard Test Method for Characterizing Semiconductor Deep Levels by Transient Capacitance Techniques (Includes all amendments And changes 3/2/2021).
Automatically translated name:
Standard Test Method for Characterizing Semiconductor Deep Levels by Transient Capacitance Techniques
STANDARD published on 10.1.2001
Designation standards: ASTM F978-90(1996)e1
Note: WITHDRAWN
Publication date standards: 10.1.2001
SKU: NS-57147
The number of pages: 8
Approximate weight : 24 g (0.05 lbs)
Country: American technical standard
Category: Technical standards ASTM
Keywords:
activation energy, deep levels, DLTS, semiconductor silicon, trap density, transient capacitance, ICS Number Code 29.045 (Semiconducting materials)
1. Scope |
This standard was transferred to SEMI (www.semi.org) May 2003 1.1 This test method covers three procedures for determining the density, activation energy, and prefactor of the exponential expression for the emission rate of deep-level defect centers in semiconductor depletion regions by transient-capacitance techniques. Procedure A is the conventional, constant voltage, deep-level transient spectroscopy (DLTS) technique in which the temperature is slowly scanned and an exponential capacitance transient is assumed. Procedure B is the conventional DLTS (Procedure A) with corrections for nonexponential transients due to heavy trap doping and incomplete charging of the depletion region. Procedure C is a more precise referee technique that uses a series of isothermal transient measurements and corrects for the same sources of error as Procedure B. 1.2 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use. |
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