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IEC 60191-6-ed.3.0
Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages
STANDARD published on 26.11.2009
The information about the standard:
Designation standards: IEC 60191-6-ed.3.0
Publication date standards: 26.11.2009
SKU: NS-409119
The number of pages: 76
Approximate weight : 228 g (0.50 lbs)
Country: International technical standard
Category: Technical standards IEC
The category - similar standards:
Annotation of standard text IEC 60191-6-ed.3.0 :
IEC 60191-6:2009 gives general rules for the preparation of outline drawings of surface-mounted semiconductor devices. It supplements IEC 60191-1 and IEC 60191-3. It covers all surface-mounted devices discrete semiconductors with lead count of greater or equal to 8, as well as integrated circuits classified as form E in Clause 3 of IEC 60191-4. This third edition of IEC 60191-6 cancels and replaces the second edition, published in 2004 and constitutes a technical revision. This edition includes the following significant changes with respect to the previous edition: a) scope is modified to cover all surface-mounted devices discrete semiconductors with lead count of greater or equal to 8; b) editorial modifications on several pages; and c) technical revision to ball grid array package (BGA) especially its geometrical drawing format. (two types of BGA would unify as one type as a result of revising drawing format. La CEI 60191-6:2009 donne les regles generales pour la preparation des dessins dencombrement des dispositifs a semi-conducteurs pour montage en surface. Elle complete la CEI 60191-1 et la CEI 60191-3. Elle couvre tous les dispositifs pour montage en surface a semi-conducteurs discrets dotes dau moins 8 sorties, ainsi que les circuits integres classes "de forme E" dans lArticle 3 de la CEI 60191-4. Cette troisieme edition de la CEI 60191-6 annule et remplace la deuxieme edition parue en 2004 dont elle constitue une revision technique. La presente edition contient les modifications majeures suivantes par rapport a ledition precedente: a) le domaine dapplication est modifie pour couvrir tous les dispositifs pour montage en surface a semi-conducteurs discrets dotes dau moins 8 sorties; b) des modifications editoriales sur plusieurs pages; et c) une revision technique du boitier matriciel a billes (BGA) particulierement son format de dessin geometrique. (la revision du format de dessin permettrait dunifier deux types de boitier BGA pour navoir quun seul type.)
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