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IEC/TR 62856-ed.1.0
Documentation on design automation subjects - The Bird´s-eye View of Design Languages (BVDL)
STANDARD published on 7.8.2013
The information about the standard:
Designation standards: IEC/TR 62856-ed.1.0
Publication date standards: 7.8.2013
SKU: NS-407968
The number of pages: 42
Approximate weight : 126 g (0.28 lbs)
Country: International technical standard
Category: Technical standards IEC
The category - similar standards:
Industrial automation systems in generalIT applications in industry
Annotation of standard text IEC/TR 62856-ed.1.0 :
IEC/TR 62856:2013 describes features for existing design languages, as well as for enhancing and newly developing design languages belonging to the defined design processes of System on a chip (SoC) which ranges from system level design, SoC design implementation and verification, IP block creation and analog block design down to interface data preparation for manufacturing. Thirty-three design languages have been chosen and each feature of their latest version as of March 2011 is reflected in this report: UML, Esterel, Rosetta, SystemC, SystemC-AMS, IBIS, CITI, TouchStone, BSDL, System Verilog, VHDL, Verilog HDL, UPF, CPF, e language, PSL, FSDB, SDC, DEF, Open Access, SDF, GDS II, OASIS, STIL, WGL, Verilog-A, Verilog-AMS, SPICE, VHDL-AMS, LEF, Liberty, CDL and IP-XACT. La CEI/TR 62856:2013 decrit des caracteristiques pour des langages de conception existants, ainsi que pour ameliorer et renouveler des langages de conception qui appartiennent aux processus de conception definis du Systeme sur puce (SoC) allant de la conception au niveau systeme, de la mise en oeuvre et de la verification SoC, de la creation de bloc IP et de la conception de bloc analogique jusqua la preparation des donnees dinterface pour la fabrication. Trente-trois langages de conception sont choisis et la derniere version de chaque langage est reprise dans le present rapport, a la date de mars 2011: UML, Esterel, Rosetta, SystemC, SystemC-AMS, IBIS, CITI, TouchStone, BSDL, System Verilog, VHDL, Verilog HDL, UPF, CPF, e language, PSL, FSDB, SDC, DEF, Open Access, SDF, GDS II, OASIS, STIL, WGL, Verilog-A, Verilog-AMS, SPICE, VHDL-AMS, LEF, Liberty, CDL et IP-XACT.
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