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VSB - Parallel Sub-system Bus of the IEC 60821 VMEbus
STANDARD published on 30.12.1988
Designation standards: IEC 60822-ed.1.0
Publication date standards: 30.12.1988
SKU: NS-411599
The number of pages: 311
Approximate weight : 964 g (2.13 lbs)
Country: International technical standard
Category: Technical standards IEC
Semiconductor devices in generalInterface and interconnection equipmentMicroprocessor systems
The VSB bus was designed to meet the needs of multiprocessor systems based on high-performance 32-bit microprocessors built up from board assemblies. lt includes a high-speed asynchronous data transfer bus allowing masters to direct the transfer of binary data to and from slaves according to 4 kinds of cycles: address-only, single-transfer, block-transfer and interrupt-acknowledge cycles. It also includes an arbitration bus enabling arbiter modules and/or requester modules to coordinate the use of the data-transfer bus according to two arbitration methods (series or parallel). Note: -For the price of this publication, please consult the ISO/IEC price-code list. Le bus VSB a ete concu pour repondre au besoin de systemes multiprocesseurs bases sur des microprocesseurs 32 bits de hautes performances et construits a partir d'ensembles de cartes. Inclut un bus asynchrone de transfert de donnees a haute vitesse qui permet a des maitres de diriger des transferts de donnees binaires vers, ou depuis, des esclaves selon quatre types de cycles: uniquement d'adressage, de transfert unique, de transfert par bloc et de reconnaissance d'interruption. Inclut egalement un bus d'arbitrage qui permet a des modules arbitres et/ou a des modules demandeurs de coordonner l'usage du bus de transfert de donnees selon deux methodes d'arbitrage (serie ou parallele). Note - Pour le prix de cette publication, veuillez consulter la liste du code-prix ISO/CEI.
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